Amplifier circuit

ABSTRACT

An amplifier circuit comprises differential amplification circuitry comprising an input stage having first and second differential inputs, and an output stage, having respective first and second amplifier components with first and second differential outputs. The first amplifier component of the output stage comprises a first power transistor operably coupled to the first differential output and driven by a first differential output of the input stage, and a third power transistor operably coupled to the first differential output of the amplifier circuit and driven by a second output of the input stage. The second amplifier component comprises a second power transistor operably coupled to the second differential output and driven by a second output of the input stage, and a fourth power transistor operably coupled to the second differential output and driven by the first output of the input stage. Each of the first and second power transistors of the first and second amplifier components is driven in a current mirror arrangement by the respective first and second output of the input stage.

FIELD OF THE INVENTION

The invention relates to an amplifier circuit, and more particularly toan amplifier circuit, and a semiconductor device comprising an amplifiercircuit. The invention is applicable to, but not limited to, asemiconductor device and an amplifier circuit comprising differentialamplification circuitry.

BACKGROUND OF THE INVENTION

It is known for electronic devices, such as mobile telephone handsetsand the like, to comprise audio functionality. Traditionally, suchelectronic devices comprise traditional electromagnetic speakercomponents that use a coil and a cone or diaphragm to convert electricalsignals into audio signals. Manufacturers of such electronic devices arecontinually striving to reduce weight and size of the devices, whilstincreasing functionality, in order to meet market demands and provide acompetitive advantage. As will be appreciated by a skilled artisan, theuse of a cone and coil within traditional electromagnetic speakersresults in these speakers being relatively bulky. Thus, traditionalelectromagnetic speakers tend to be one of the most problematic featureswhen trying to minimise the size and weight of devices incorporatingsuch traditional speaker components.

Piezo-ceramic flat speakers are known, to use a ceramic disk glued to amembrane to convert electrical signals into audio signals. Consequently,such piezo-ceramic flat speakers comprise a substantially reducedthickness, compared to traditional electromagnetic speakers, for examplein a region of 0.8 mm, which is approximately one fifth that of thethinnest traditional electromagnetic speakers. Furthermore, suchpiezo-ceramic flat speakers are light weight. Advancements inpiezo-ceramic technology have resulted in piezo-ceramic speakers beingcapable of meeting the standards of audio reproduction required forelectronic devices, such as mobile telephone handsets, whilst alsoenabling a reduction in size and weight of such devices. Piezo-ceramicspeakers also provide the additional benefits of low energy requirementsat low frequencies, and higher acoustic output compared toelectromagnetic speakers (in the order of 60%).

Class D amplifiers are well known in the art, and are generally deemedsuitable for driving electromagnetic speakers. Class D amplifiers useswitching technology to achieve high power efficiency. In particular,electromagnetic speakers typically present a relatively high impedance(e.g. 100Ω) at the operating frequency of the Class D amplifier (e.g. 1MHz). However, the impedance of piezo-ceramic speakers is a purelycapacitive reactance. Consequently, Class D amplifiers are unsuitablefor driving piezo-ceramic speakers, since their impedance is close tothat of a short circuit at the operating frequency of a Class Damplifier.

Instead, linear amplification design is required to drive piezo-ceramicspeakers, such as provided by a Class AB amplifier.

FIG. 1 illustrates an example of conventional amplifier circuitry 100for converting a single ended signal at an output of a Programmable GainAmplifier (PGA) 110 into a differential signal applied to a speaker 120,such as a piezo-ceramic speaker. The amplifier circuitry 100 comprises aSingle to Differential (S2D) amplifier circuit 130 and two single endedClass AB linear power amplifier circuits 140, 150. Unfortunately, forelectronic devices such as mobile telephone handsets, the use of threeamplifier circuits requires a large silicon area, which is undesirablewhen silicon area is at a premium, due to a need to reduce the cost ofsuch devices to meet market demands.

In addition, each amplifier circuit contributes independently to theoutput noise of the amplifier circuitry, resulting in a relatively highnoise floor. Furthermore, the use of three amplifiers circuits resultsin a large quiescent current, requiring complex quiescent currentcontrol circuitry. Consequently, the use of three amplifier circuits, inthis manner, to provide the linear amplification required forpiezo-ceramic speakers is undesirable.

A further problem with conventional single ended Class AB linear poweramplifier circuits 140, 150 is that their input stages are typicallyrequired to have rail-to-rail capability, e.g. capability for thevoltage of the output nodes of the input stage to reach the levels ofsupply and ground rails in order to efficiently drive the powertransistors of the output stages. As a result, a folded-cascodestructure, as illustrated in FIG. 1B, is typically used for the inputstage, resulting in a high component count as well as requiringadditional silicon area. A folded-cascode structure is a differentialamplifier stage in which additional branches allow the output node tohave a larger voltage swing capability.

WO1991/007814 describes an amplifier that has a folded-cascode inputstage, an AB class output stage, a first common mode feedback circuitthat stabilizes the input stage and a second common mode feedbackcircuit that stabilizes the output stage. Ten capacitors are needed forfrequency compensation, which results in a very area-consuming solution.This amplifier is not adapted to low supply voltages (it is suppliedwith 5V) because the class AB function is achieved due to atransconductance stage that requires a relatively large voltageheadroom. Quiescent current control is achieved by component matchingonly and there is no minimal current regulation, which is detrimental tothe Total Harmonic Distortion.

Thus, a need exists for an improved semiconductor device with anamplifier circuit where at least some of the aforementioneddisadvantages with prior art arrangements are substantially alleviated.

SUMMARY OF THE INVENTION

In accordance with aspects of the invention, there is provided anamplifier circuit and a semiconductor device with an amplifier circuitas defined in the appended Claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates an example of conventional amplification circuitry,with FIG. 1B illustrating conventional miller OperationalTransconductance Amplifier (OTA) and a folded cascode OTA circuit usedtherein.

Exemplary embodiments of the invention will now be described, by way ofexample only, with reference to the accompanying drawings, in which:

FIG. 2 illustrates a semiconductor device in accordance with someembodiments of the invention.

FIG. 3 illustrates an example of an amplifier circuit according to anembodiment of the invention.

FIG. 4 illustrates an amplifier circuit comprising differentialamplification circuitry according to an embodiment of the invention.

FIG. 5 illustrates an amplifier circuit comprising quiescent currentcontrol loop circuitry according to an embodiment of the invention.

FIG. 6 illustrates an amplifier circuit comprising common mode voltagecontrol circuitry according to an embodiment of the invention.

FIG. 7 illustrates an amplifier circuit comprising the differentialamplification circuitry, quiescent current control circuitry and commonmode control voltage circuitry of FIG's 4 to 6 according to anembodiment of the invention.

DESCRIPTION OF EMBODIMENTS

Embodiments of the invention will be described in terms of amplifiercircuitry in a semiconductor device for converting a single ended signalat an output of a Programmable Gain Amplifier (PGA) into a differentialsignal applied to a speaker, such as a piezo-ceramic speaker.

Although embodiments of the invention will be described in terms ofamplification circuitry for converting a single ended signal into adifferential signal (generally referred to as single-to-differentialamplification), it will be appreciated that the inventive concept mayequally be applied to differential-to-differential signal amplificationcircuitry. Furthermore, although embodiments of the invention will bedescribed in terms of amplification circuitry within electronic devices,for example mobile telephone handsets, it will be appreciated that theinventive concept herein described may be embodied in any apparatus thatincorporates amplification circuitry.

In summary, the inventive concept proposes an amplifier circuit, and asemiconductor device comprising such an amplifier circuit, where theamplifier circuit comprises differential amplification circuitry, thedifferential amplification circuitry comprising an input stage and anoutput stage. The input stage is operably coupled to first and seconddifferential inputs of the amplifier circuit. The output stage isoperably coupled to first and second differential outputs of theamplifier circuit, and comprises first and second amplifier components.The first amplifier component of the output stage comprises a firstpower transistor operably coupled to the first output of the amplifiercircuit and driven by a first output of the input stage, and a secondpower transistor operably coupled to the first output of the amplifiercircuit and driven by a second output of the input stage. The secondamplifier component comprises a first power transistor operably coupledto the second output of the amplifier circuit and driven by the secondoutput of the input stage, and a second power transistor operablycoupled to the second output of the amplifier circuit and driven by thefirst output of the input stage. Each of the first power transistors ofthe first and second amplifier components is driven by the respectiveoutput of the input stage in a current mirror fashion.

Referring now to FIG. 2, there is illustrated a semiconductor device 200in accordance with some embodiments of the invention. For the embodimentillustrated in FIG. 2, the semiconductor device 200 comprises circuitryarranged to convert a single ended signal at an output of a ProgrammableGain Amplifier (PGA) 210 into a differential signal for a speaker 220,such as a piezo-ceramic speaker. The semiconductor device 200 comprisesan amplifier circuit 230, such as a class AB linear amplifier circuit.The use of only a single amplifier circuit, as opposed to three in aconventional amplifier circuitry, significantly reduces the requiredsilicon area, and results in a lower quiescent current and a relativelylow noise floor. VAG is a reference voltage and is set generally to halfof the supply rail voltage.

Referring now to FIG. 3, there is illustrated an example of theamplifier circuit 230 according to an embodiment of the invention. Theamplifier circuit 230 comprises first and second differential inputsvip, vim, and first and second differential outputs vop, vom. Theamplifier circuit 230 further comprises differential amplificationcircuitry 310 for amplifying differential signals received at thedifferential inputs vip, vim and providing the amplified signals to thedifferential outputs vop, vom.

Furthermore, for the illustrated embodiment, the amplifier circuit 230further comprises common mode voltage control in a form of variableoffset buffers 330, located between the outputs 410, 420 of the inputstage and the first power transistors M8, M9 of the amplifier componentsof the output stage. More particularly, for the illustrated embodiment,the variable offset buffers 330 are located between the outputs 410, 420of the input stage and the current mirrors 450, 460 of the amplifiercomponents of the output stage, and are controlled by output common modefeedback, as described further with respect to FIG. 6.

Referring now to FIG. 4, there is illustrated the differentialamplification circuitry 310 of the amplifier circuit 230, comprising aninput stage and an output stage, according to an embodiment of theinvention. The output stage of differential amplification circuitry 310comprises first and second amplifier components. The first amplifiercomponent, illustrated by heavy lines in FIG. 4 for clarity, comprises afirst power transistor M8 operably coupled to the first output vop ofthe amplifier circuit 230 and driven by a first output 410 of the inputstage, and a second power transistor M4 operably coupled to the firstoutput vop of the amplifier circuit 230 and driven by a second output420 of the input stage. The second amplifier component comprises a firstpower transistor M9 operably coupled to the second output vom of theamplifier circuit 230 and driven by the second output 420 of the inputstage, and a second power transistor M3 operably coupled to the secondoutput vom of the amplifier circuit 230 and driven by the first output410 of the input stage.

Each of the first power transistors M8, M9 of the first and secondamplifier components is driven by the respective outputs 410, 420 of theinput stage in a current mirror fashion. Accordingly, the firstamplifier component further comprises transistors M5 and M7, operablycoupling the first output 410 of the input stage to the power transistorM8, and enabling the first output 410 of the input stage to drive thepower transistor M8 in a current mirror fashion. Similarly, the secondamplifier component further comprises transistors M6 and M10, operablycoupling the second output 420 of the input stage to the powertransistor M9 in current mirror fashion. For the embodiment illustrated,transistors M7, M8, M9 and M10 each comprise a P-Channel Metal OxideSemiconductor Field Effect Transistor (PMOS). Conversely, transistorsM3, M4, M5 and M6 each comprise an N-Channel Metal Oxide SemiconductorField Effect Transistor (NMOS).

Each of the amplifier components utilise both outputs 410, 420 of theinput stage to drive the outputs vop, vom of the amplifier circuit 230.In this manner, the outputs vop, vom of the amplifier circuit 230 may bedriven in a substantially balanced manner. Furthermore, by driving thepower transistors M8 and M9 in a current mirror fashion, the input stageis not required to have a rail-to-rail capability in order to be able toefficiently drive the power transistors M8 and M9.

For the illustrated embodiment, the input stage of differentialamplification circuitry 310 comprises a conventional Miller OperationalTransconductance Amplifier (OTA) comprising a first transistor M1 and asecond transistor M2, providing a substantially matched transistor pairoperably coupling the first and second differential inputs vip, vim tothe first and second outputs 410, 420 respectively of the input stage.For the embodiment illustrated, transistors M1 and M2 each comprise aP-Channel Metal Oxide Semiconductor Field Effect Transistor (PMOS). Thegates for transistors M1 and M2 are connected to inputs vip, vimrespectively, and the drains for transistors M1 and M2 are connected tothe outputs 410, 420 respectively of the input stage. The sources fortransistors M1 and M2 are both connected to a current source 430.Outputs 410, 420 of the input stage are further connected to currentsinks 440.

As will be appreciated by a skilled artisan, the use of a Miller OTA forthe input stage results in a reduced component count compared to afolded-cascode structure, thereby resulting in lower component costs anda reduced silicon area requirement.

Although this embodiment has utilised a Miller OTA for the input stage,it is envisaged in other embodiments of the invention that alternativeinput stage configurations may be employed.

When a differential signal, such as an audio signal, is present atinputs vip, vim, the input stage, or more particularly transistors M1and M2, amplify the difference, or error, between the two inputs vip,vim.

In the case where a low (e.g. negative) voltage is present at one of theinputs vip, vim, this low voltage is communicated to the gate of thecorresponding PMOS transistor M1, M2, allowing current from the currentsource 430, to flow through the transistor, the lower the voltagepresent at the gate of the transistor, the more current flowing throughthe transistor, and thus the higher the voltage at the correspondingoutput 410, 420 of the input stage.

Conversely, in a case where a high voltage is present at one of theinputs vip, vim, this high voltage is communicated to the gate of thecorresponding PMOS transistor M1, M2, thereby restricting current fromthe current source 430 from flowing through the transistor, the higherthe voltage present at the gate of the transistor, the lower the currentflowing through the transistor, and thus the lower the voltage at thecorresponding output 410, 420 of the input stage.

Taking as an example a case where a lower voltage is present at thefirst input vip of the amplifier circuit 230, and a higher voltage ispresent at the second input vim of the amplifier circuit 230, the firstoutput 410 of the input stage will have a relatively higher voltagelevel than that of the second output 420 of the input stage. As will beappreciated by a skilled artisan, the greater the difference between thevoltages present at the inputs vip, vim the greater the amplifieddifference between the voltages at the outputs 410, 420 of the inputstage.

As previously mentioned, the output stage of the differentialamplification circuitry 310 comprises first and second amplifiercomponents, each amplifier component comprising a first power transistorM8, M9 operably coupled to an output vop, vom of the amplifier circuit230, and driven by an output 410, 420 of the input stage in a currentmirror fashion, via transistors M5, M6, M7 and M10. In particular, thegates of NMOS transistors M5 and M6 are connected to the outputs 410,420 of the input stage, and the source of each transistor M5 and M6 isconnected to a negative power rail Vss. The drains of transistors M5 andM6 are connected to the drains of PMOS transistors M7 and M10respectively, the sources for which are connected to a positive powerrail vdd. The gates of transistors M7 and M10 are connected by theirrespective drains, and to the gates of PMOS transistors M8 and M9. Thesources of transistors M8 and M9 are also connected to the positivepower rail vdd, and the drains of the transistors M8 and M9 areconnected to outputs vop, vom of the amplifier circuit 230 respectively.In this manner, transistors M5, M7 and M8, and transistors M6, M9 andM10 provide common source NMOS and PMOS current mirrors 450, 460 foreach amplifier component of the output stage, via which the first powerPMOS transistors M8, M9 are driven by the respective outputs 410, 420 ofthe input stage.

For each amplifier component, in a case where the output 410, 420 of theinput stage by which the current mirror 450, 460, is driven has a highvoltage, this high voltage is communicated to the gate of the NMOStransistor M5, M6 of that current mirror 450, 460, thereby allowingcurrent flow there through. In this manner, the voltage at the gate ofthe power transistor M8, M9 of the current mirror 450, 460 is pulleddown towards the negative power rail vss, allowing current to flowthrough the transistor M8, M9, and thus to the output vop, vom of theamplifier circuit 230. As will be appreciated by a skilled artisan, thehigher the voltage at the output 410, 420 of the input stage, the higherthe current flowing through the power transistor M8, M9 and thus thehigher the current flowing to the output vop, vom of the amplifiercircuit 230.

Conversely, in a case where the output 410, 420 of the input stage bywhich the current mirrors 450, 460 is driven has a low voltage, this lowvoltage is communicated to the gate of NMOS transistor M5, M6 of thatcurrent mirror 450, 460, thereby restricting current flow there through.In this manner, the voltage at the gate of the power transistor M8, M9of the current mirror 450, 460 is pulled up towards the positive powerrail vdd, thereby restricting current flow through the transistor M8,M9, and thus to the output vop, vom of the amplifier circuit 230. Aswill be appreciated by a skilled artisan, the lower the voltage at theoutput 410, 420 of the input stage, the lower the current flowingthrough the power transistor M8, M9, and thus the lower the currentflowing to the output vop, vom of the amplifier circuit 230.

As also previously mentioned, each amplifier component further comprisesa second power amplifier transistor M4, M3 operably coupled to an outputvop, vom of the amplifier circuit 230, and driven by an output 410, 420of the input stage. In particular, the gates of NMOS power transistorsM3, M4 are connected to the outputs 410, 420 respectively of the inputstage, and the source of each transistor M4, M3 is connected to thenegative power rail vss. The drains of transistors M4, M3 are connectedto outputs vop, vom of the amplifier circuit 230 respectively,Compensation capacitors C1, C2 are provided between the drains and gatesof transistors M3, M4 respectively, and create a dominant pole for thedifferential amplification circuitry 310.

For each amplifier component, in the case where the output 410, 420 ofthe input stage by which the NMOS power transistor M4, M3 is driven, hasa high voltage, this high voltage is communicated to the gate of thetransistor M4, M3, thereby allowing current flow there through. In thismanner, the voltage at the output vop, vom of the amplifier circuit 230is pulled down towards the negative power rail vss (noting thatincreased current flow through M3, M4 is the cause, not the consequence,of the Vop, Vom voltage drop). As will be appreciated by a skilledartisan, the higher the voltage at the output 410, 420 of the inputstage, the higher the current flowing through the transistor M3, M4respectively.

Conversely, in a case where the output 410, 420 of the input stage bywhich the NMOS power transistor M4, M3 is driven has a low voltage, thislow voltage is communicated to the gate of the transistor M4, M3,thereby restricting current flow there through. In this manner, thevoltage at the output vop, vom of the amplifier circuit 230 is pulleddown towards the negative power rail vss to a significantly lesserdegree. As will be appreciated by a skilled artisan, the lower thevoltage at the output 410, 420 of the input stage, the lower the currentflowing through the transistor M3, M4 respectively.

Referring back to the example above, where a lower voltage is present atthe first input vip of the amplifier circuit 230, and a higher voltageis present at the second input vim of the amplifier circuit 230, thefirst output 410 of the input stage will have a relatively highervoltage level than that of the second output 420 of the input stage.

As a consequence, since the first output 410 drives the current mirror450 of the first amplifier component of the output stage, the highvoltage at the first output 410 causes current to be allowed to flowthrough the power transistor M8 of the current mirror 450, therebycausing current to flow to the output vop of the amplifier circuit 230.Meanwhile, the low voltage at the second output 420 causes transistor M4to hinder current flow there through. Consequently, the current flowingthrough transistor M8 causes a high voltage at the output vop.

Conversely, since the second output 420 drives the current mirror 460 ofthe second amplifier component of the output stage, the low voltage atthe second output 420 restricts current flowing through the powertransistor M9 of the current mirror 460. Meanwhile, the high voltage atthe first output 410 causes transistor M3 to allow current flow therethrough. Consequently, current is drawn from the output vom, causing alow voltage at the output vom.

As will be appreciated by a skilled artisan, both of the amplifiercomponents within the output stage each use both outputs 410, 420 fromthe input stage, such that current sourced by power transistors M8 andM9 passes through the load and is sunk by power transistors M3, M4. Inthis manner, the load is advantageously driven in a balanced operation.

Referring back to FIG. 3, for the illustrated embodiment the amplifiercircuit 230 further comprises quiescent current control loop 320,arranged to control the current sinks 440, and thereby provide quiescentcurrent regulation to the outputs 410, 420 of the input stage of thedifferential amplification circuitry 310. The quiescent currentregulation loop is intended to regulate the current flowing in powertransistors M8, M9, M3 and M4 when the amplifier is in a quiescent state(for example when the amplifier is enabled, but there is no audio signalat its input). The goal of the quiescent current regulation loop is tocontrol the current consumption of the amplifier when no audio signal ispresent at the input, to avoid wasting energy. The quiescent currentregulation loop also ensures that a minimum current flows through thepower transistors that would otherwise be completely turned ‘off’ by thedifferential amplifier circuitry when an audio signal of sufficientamplitude is present at the amplifier input. This minimum current flowhelps to minimize the non-linearity of the power transistor, which isbeneficial to the harmonic distortion performance of the amplifier.

Referring now to FIG. 5, there is illustrated the quiescent currentcontrol loop 320 in greater detail, according to an embodiment of theinvention. The quiescent current regulation loop operates as follows:images of the output current in M4 and M3 are produced, thanks to M44and M33 respectively. The minimum of these two images is extracted bythe mean of the translinear bjt circuit 510. I0=Iref generates a voltagereference through T5 and T6 and the translinear circuit will produce thesame voltage as this reference (Iref) if the copied (image) currents inM33 and M44 match the Iref current. If the copied (image) currents inM33 and M44 do not match the Iref current, a voltage error is producedand amplified through the M14/M15 differential stage.

The quiescent current control loop 320 comprises quiescent currentsensing components, which for the illustrated embodiment comprise NMOStransistors M33 and M44. The gates of transistors M33 and M44 areconnected to the outputs 410, 420 respectively of the input stage, andthe source of each transistor M33, M44 is connected to the negativepower rail vss.

The drains of transistors M33, M44 is connected to a translinear loop510, which for the illustrated embodiment comprises NPN and PNP bipolartransistors T1 to T6. Translinear loop 510 provides minimum quiescentcurrent functionality. The translinear loop 510 converts the current inM44/M33 into voltage information, for example M44 catches an image ofthe current flowing in M4 and this current is forwarded to thediode-mounted bi-polar junction transistor (BJT) T2 (which is a devicematched to the reference transistor T5).

If, for example, the current in T2 is lower than the current in T1, thenode to which emitters of T3 and T4 are connected will be driven by T4because the base-emitter voltage of T3 will be smaller than thebase-emitter voltage of T4. Consequently T3 will be turned ‘off’. Thewhole lo current will then flow into T4. As T4 is matched to T6, thebase-emitter voltage of T4 will be equal to the base-emitter voltage ofT6. Hence, the difference between the M14 gate voltage and the M15 gatevoltage will be equal to the difference between the base-emitter voltageof T5 (in which lo flows) and the base-emitter voltage of T2 (in whichflows M44 current, a copy of M4 current).

If the M44 current is smaller than lo, then the gate voltage of M14 willbe higher than the gate voltage of M15. Hence, the current flowingthrough M14 and M13 will decrease. By current mirroring, the currentsunk by M11 and M12 will decrease as well, which will raise the voltageat the differential outputs 410 and 420. This results in an increase ofthe current in M4 and M44 until M44 current reaches lo. Outputs of thetranslinear loop 510 are provided to gates of differential transistorpair M14/M15, which in turn drive, and thereby regulate, current sinktransistors M11, M12 (providing the functionality of current sinks 440)via transistor M13. In the same way as for the differentialamplification circuitry 310, capacitors C1 and C2 create a dominant polefor the quiescent current control loop 320. The quiescent currentcontrol loop 320 shares the same high impedance nodes as thedifferential outputs 410 and 420. As a consequence, any compensationscheme made for the differential amplification will be shared also bythe quiescent current loop, which is a major advantage regarding siliconarea savings as a designer no longer needs to add bulky capacitors tocompensate specifically the quiescent current loop.

If the drain currents of both sensing transistors M33 and M44 increase,indicating a high quiescent current, the current flowing through bothM33 and M44 will also increase, causing the translinear loop to decreasethe voltage presented to the gate of PMOS transistor M14. The decreasein the gate voltage of transistor M14 causes the current flowing throughtransistor M14 to increase, which in turn increases the drain currentsof current sink transistors M11 and M12. As a result, the current flowthrough transistors M11 and M12 is increased, which decreases thevoltage at the outputs 410, 420 of the input stage, correcting thequiescent current in power transistors M3 and M4.

In the presence of an input signal at the inputs vip, vim of theamplifier circuit 230, transistors M1 and M2 differentially drive theoutputs 410, 420 of the input stage. If, for example, the current at thegate of transistor M33 is increased, and the current at the gate oftransistor M44 is decreased, the translinear loop 510 regulates thedrain current of M44 to a minimum value. In this manner, the gatevoltage of transistors M11 and M12 is decreased, strengthening theincrease in the voltage at the first output 410 of the input stage,whilst preventing the voltage at the second output 420 of the inputstage from dropping below a minimum voltage, thereby regulating aminimum quiescent current in transistors M4, M44 and M6. By regulating aminimum quiescent current in this manner, cross-over distortion may beadvantageously substantially eliminated.

The quiescent current regulation is advantageously independent of thevoltages at the outputs vop, vom of amplifier circuit 230 due to thesensing and regulation of quiescent current being performed at theoutputs 410, 420 of the input stage. In contrast to prior art circuits,quiescent current regulation is achieved by sensing and regulatingcurrents in power transistors M3 and M4 (NMOS only). The quiescentcurrent in PMOS power transistors (M8 and M9) does not need to beregulated, since it is set by the power NMOS current through currentmirroring. In prior art circuits, the quiescent current regulationcircuits are more complex and require much more silicon area due to theneed to sense and regulate the currents in both NMOS and PMOS powertransistors

Referring now to FIG. 6, there is illustrated the variable offsetbuffers (for example buffers 330 from FIG. 3), each in a form oftransistor pair M20/M21 and M22/M23, and common mode control loop 610providing output common mode feedback, according to an embodiment of theinvention. Resistor pair R1/R2, located between the outputs vop, vom ofamplifier circuit 230, provides an input signal vcm to the common modecontrol loop 610. The common mode control loop 610 comprises adifferential NMOS transistor pair M16, M17, the gates of which areconnected to the voltage control mode input signal vcm and a voltagereference signal vcm_ref respectively. The transistor pair M16, M17,along with transistors M24 and M25, amplify a difference (error) betweenthe voltage control mode input signal vcm and a voltage reference signalvcm_ref, and provide this amplified difference (error) voltage to gatesof transistors M18 and M19, which provide control currents to thevariable offset buffers 330.

The common mode voltage regulation is provided in the following manner.Let us suppose that vop and vom average voltage is lower than the commonmode voltage reference (VAG=vcm_ref). That is to say (vop+vom)/2<VAG.This will create a negative error at the input of the correspondingerror amplifier 610, thereby inducing a higher gate drive on M18 and M19and inducing a positive offset in the variable offset buffers 330. As aconsequence, M9 will source more current than sinked by M3. In parallel,M8 will source more current than the current sinked by M4. vop and vomwill then rise together, thereby reducing consequently the initialcommon voltage error.

For the illustrated embodiment, each variable offset buffer comprises apair of PMOS transistors M20/M21, M22/M23. The gates of transistors M20and M22 are connected to the outputs 410, 420 of the input stagerespectively, whilst the gates of transistors M21 and M23 are connectedto the gates of transistors M5 and M6 respectively. The drains oftransistors M20 and M22 are connected to the negative power rail vss,whilst the drains of transistors M21 and M23 are connected to constantcurrent sinks 620, 630. The sources of transistors M20 and M22 areconnected to the sources of transistors M21 and M23 respectively, aswell as to the outputs of the common mode control loop 610. Compensationcapacitors C3, C4 are provided between the gates of transistors M18 andM19, and the outputs vop, vom respectively, and create a dominant polefor the common mode control loop 610.

The voltage across the gate and source of transistor M5 (M5 _(vgs)) andthe voltage across the gate and source of transistor M6 (M6 _(vgs)) maybe represented as follows: —M5_(vgs) =M3_(vgs)+(M20_(vgs) −M21_(vgs))M6_(vgs) =M4_(vgs)+(M22_(vgs) −M23_(vgs))

Note that M21 vgs and M23 vgs are constant as the current through M21and M23 is constant, set by the current sinks 620 and 630.

In this manner, the variable offset buffers advantageously enable thedisassociation of the drain currents of power PMOS transistors M8 and M9from the drain currents of the power NMOS transistors M3 and M4respectively. This disassociation of the PMOS currents from the NMOScurrents makes common mode voltage regulation possible. If the amplifieris in a quiescent state (e.g. no input audio signal) and if the gates ofM3 and M4 are directly connected to the gates of M5 and M6 (e.g. novariable offset buffers), any mismatch between the currents in the powerPMOS (M8 and M9) and the power NMOS (M3 and M4) (for instance due tomanufacturing tolerances) results in a common mode error at theamplifier output. For instance, if M8 and M9 provide a slightly highercurrent than the current that is sunk by M3 and M4 in the absence ofaudio signal, then both vop and vom will increase above vcm_ref. Notethat the differential loop only ensures that vop=vom when no inputsignal is present. As a consequence of having the variable offsetbuffers, the currents of M8 and M9 may be decreased independently of M3and M4 currents, which enable a correct common mode value for theoutputs to be restored.

In an absence of an input signal at the inputs vip, vim of the amplifiercircuit 230, and if component matching is ideal, the common mode controlloop 610 forces the voltage across the gate and source of transistor M20to be equal to that of transistor M21, by driving a current twice thatof current sink 620 through transistor M18. Similarly, the common modecontrol loop 610 forces the voltage across the gate and source oftransistor M22 to be equal to that of transistor M23, by driving acurrent twice that of current sink 630 through transistor M19.

In a case where the voltages at both outputs vop, vom of the amplifiercircuit 230 are both low, the voltage control mode input signal vcm islower than the voltage reference signal vcm_ref. Consequently, the gatedrive of both transistors M18 and M19 is increased to increase the draincurrents for transistors M20 and M22 respectively. In this manner, thegate drive of transistors M5 and M6 is increased relative to that oftransistors M3 and M4 respectively. As a result, power PMOS transistorsM8 and M9 source a higher current than M3 and M4, correcting the commonmode output voltage.

Any mismatch affecting the NMOS transistors (M3/M5/M4/M6) and/or thePMOS transistors (M7/M8/M9/M10) of the output stage is advantageouslycorrected by substantially simultaneous action of the differentialamplification circuitry 310, the common mode control loop 610 and thevariable offset buffers 330, and does not result in output voltageerrors. Consequently, component matching is not critical, and so each ofthe NMOS and PMOS power transistors (M3 to M10) may have minimum channellength. M8/M9 and M3/M4 are the output devices, sometimes referred to as‘pass devices’ because in power amplification those devices need a highcurrent capability. This leads to a high Width/Length ratio. Thus, usinga minimum channel length (L=Lmin) advantageously results in aconsiderable silicon area saving.

FIG. 7 illustrates a more detailed configuration of the amplifiercircuit 230 of FIG. 3, comprising the differential amplificationcircuitry 310 of FIG. 4, the quiescent current control loop 320 of FIG.5, and the common mode control loop 610 of FIG. 6. The differentialamplification circuitry 310, quiescent current control loop 320 andcommon mode control loop 610 act substantially concurrently to regulatethe outputs vop, vom, the common mode voltage and the quiescent currentof the amplifier circuit 230, thereby providing a compact, differentialclass AB linear amplifier comprising a lower component count andrequiring a small silicon area, whilst improving noise and currentconsumption.

Furthermore, and advantageously, the amplifier circuit 230 requires onlyfour compensation capacitors, two for the differential amplificationcircuitry and quiescent current control loop (C1, C2), and two for thecommon mode control loop (C3, C4). Since conventional amplificationcircuitry typically requires a minimum of six compensation capacitors, afurther saving in terms of component count and area is achieved.

Additionally, the supply of power to the output stage of the amplifiercircuit 230 may furthermore be separated from the supply of power to theinput stage, thereby facilitating the implementation of the outputstage, combined with a DC/DC converter, for improved efficiency. If theamplifier is supplied from the battery, for example, the output powerdevices will see a higher Vds compared to a DC/DC application. The powerwasted in these devices would be then higher thereby resulting in lowerefficiency.

As the output stage is the most power consuming stage, supplying otherstages with the DC/DC converters would not improve the efficiency asthey use much lower current. Moreover, using the DC/DC converter tosupply the input would bring high frequency noise to sensitive analogueparts of the amplifier. This high frequency noise could disturb theoperation of the amplifier, resulting in higher output noise and/ordegraded Total Harmonic Distortion.

Referring back to FIG. 2, it can be seen that a further advantageprovided by the use of a single amplifier circuit 230 is that only asingle resistive feedback network, comprising resistors R1, R2, R3 andR4 is required, as opposed to two resistive feedback networks for theconventional amplification circuitry of FIG. 1, thereby providing afurther reduction in the component count and the required silicon area.

It is envisaged that the inventive concept is not limited to anamplifier circuit, and a semiconductor device comprising an amplifiercircuit, for use within electronic devices such as mobile telephonehandsets. It is also envisaged that the inventive concept is not limitedto an amplifier circuit, and a semiconductor device comprising anamplifier circuit, for providing a differential signal to a speaker,such as a piezo-ceramic speaker. It is envisaged that the inventiveconcept may be applied to any linear amplifier, such as a class ABamplifier where a differential output, high speed and/or high slew ratepower amplifier is desirable, such as a Digital Subscriber Line (xDSL),line driver (twisted pair), or a video amplifier (video composite) maybe used. Furthermore, the inventive concept is not limited toimplementation within a class AB amplifier.

It will be understood that the amplifier circuit and semiconductordevice comprising the amplifier circuit, as described above, aim toprovide at least one or more of the following advantages:

-   -   (i) a single amplifier circuit, requiring only a single        resistive feedback network and a single output stage quiescent        current control circuit, resulting in lower component count,        reduced silicon area, reduced noise and reduced quiescent        current;    -   (ii) use of a Miller OTA, resulting in lower component count,        reduced silicon area, reduced noise and reduced quiescent        current.    -   (iii) a reduction in the number of compensation capacitors        required, resulting in reduced silicon area and a lower        component count.

In particular, it is envisaged that the aforementioned inventive conceptcan be applied by a semiconductor manufacturer to any integrated circuitarchitecture supporting an improved amplifier circuit. It is furtherenvisaged that, for example, a semiconductor manufacturer may employ theinventive concept in a design of a stand-alone device, orapplication-specific integrated circuit (ASIC) and/or any othersub-system element employing an integrated circuit to support animproved amplifier circuit.

It will be appreciated that any suitable distribution of functionalitybetween different functional units or controllers, may be used withoutdetracting from the inventive concept herein described. Hence,references to specific functional devices or elements are only to beseen as references to suitable means for providing the describedfunctionality, rather than indicative of a strict logical or physicalstructure or organization.

The elements and components of an embodiment of the invention may bephysically, functionally and logically implemented in any suitable way.Indeed, the functionality may be implemented in a single unit or IC, ina plurality of units or ICs or as part of other functional units.

Although the inventive concept has been described in connection withsome embodiments, it is not intended to be limited to the specific formset forth herein. Rather, the scope of the invention is limited only bythe accompanying claims. Additionally, although a feature may appear tobe described in connection with particular embodiments, one skilled inthe art would recognize that various features of the describedembodiments may be combined in accordance with the invention. In theclaims, the term ‘comprising’ does not exclude the presence of otherelements or steps.

Furthermore, although individual features may be included in differentclaims, these may possibly be advantageously combined, and the inclusionin different claims does not imply that a combination of features is notfeasible and/or advantageous. Also, the inclusion of a feature in onecategory of claims does not imply a limitation to this category, butrather indicates that the feature is equally applicable to other claimcategories, as appropriate.

Furthermore, the order of features in the claims does not imply anyspecific order in which the features must be performed and in particularthe order of individual steps in a method claim does not imply that thesteps must be performed in this order. Rather, the steps may beperformed in any suitable order. In addition, singular references do notexclude a plurality. Thus, references to ‘a’, ‘an’, ‘first’, ‘second’etc. do not preclude a plurality.

Thus, an improved amplifier circuit, and semiconductor device comprisingan amplifier circuit have been described, where the aforementioneddisadvantages with prior art arrangements have been substantiallyalleviated.

The invention claimed is:
 1. A linear amplifier circuit comprises:differential amplification circuitry comprising: an input stage havingfirst and second differential inputs, and an output stage, havingrespective first and second amplifier components with first and seconddifferential outputs; wherein the first amplifier component of theoutput stage comprises: a first power transistor operably coupled to thefirst differential output and driven by a first differential output ofthe input stage, and a third power transistor operably coupled to thefirst differential output of the amplifier circuit and driven at acontrol electrode by a voltage at a second output of the input stage,wherein the second amplifier component comprises: a second powertransistor operably coupled to the second differential output and drivenby a second output of the input stage, and a fourth power transistoroperably coupled to the second differential output and driven at acontrol electrode by a voltage at the first output of the input stage;wherein each of the first and second power transistors of the first andsecond amplifier components is driven in a current mirror arrangement bythe respective first and second output of the input stage.
 2. The linearamplifier circuit of claim 1 wherein the input stage comprises a firsttransistor and a second transistor arranged to provide a matchedtransistor pair operably coupling the first and second differentialinputs to the respective first and second outputs of the input stage. 3.The linear amplifier circuit of claim 2 wherein the first and secondtransistors of the input stage each comprise a P-Channel Metal OxideSemiconductor Field Effect Transistor.
 4. The linear amplifier circuitof claim 2 wherein the first and second power transistors of the firstand second amplifier components each comprise a P-Channel Metal OxideSemiconductor Field Effect transistor, and the third and fourth powertransistors of the first and second amplifier components each comprisinga N-Channel Metal Oxide Semiconductor Field Effect transistor.
 5. Thelinear amplifier circuit of claim 2 wherein the first and second outputsof the input stage are connected to the current sinks.
 6. The linearamplifier circuit of claim 2, wherein a common mode voltage control loopprovides output common mode feedback to variable offset buffers andlocated between the first and second outputs of the input stage and thefirst and second power transistors of the output stage.
 7. The linearamplifier circuit of claim 1 wherein the first and second powertransistors of the first and second amplifier components each comprise aP-Channel Metal Oxide Semiconductor Field Effect transistor, and thethird and fourth power transistors of the first and second amplifiercomponents each comprising a N-Channel Metal Oxide Semiconductor FieldEffect transistor.
 8. The linear amplifier circuit of claim 7 whereinthe first and second amplifier components of the output stage eachcomprise a common source NMOS PMOS current mirror, via which the firstand second power transistors are driven by the respective first andsecond outputs of the input stage.
 9. The linear amplifier circuit ofclaim 1 wherein the first and second outputs of the input stage areconnected to the current sinks.
 10. The linear amplifier circuit ofclaim 9 wherein the current sinks comprise N-Channel Metal OxideSemiconductor Field Effect transistors.
 11. The linear amplifier circuitof claim 9 wherein the amplifier circuit further comprises a quiescentcurrent control loop, arranged to regulate the current sinks.
 12. Thelinear amplifier circuit of claim 11, wherein the quiescent currentcontrol loop comprises quiescent current sensing components connected tothe outputs of the input stage.
 13. The linear amplifier circuit ofclaim 12, wherein the quiescent current control loop further comprises atranslinear loop connected to the quiescent current sensing components.14. The linear amplifier circuit of claim 13 wherein outputs of thetranslinear loop are provided to a differential transistor pair, whichin turn drive the current sinks.
 15. The linear amplifier circuit ofclaim 1, wherein a common mode voltage control loop provides outputcommon mode feedback to variable offset buffers and located between thefirst and second outputs of the input stage and the first and secondpower transistors of the output stage.
 16. The linear amplifier circuitof claim 15 wherein the common mode control loop comprises a resistorpair, located between the first and second differential outputs arrangedto provide an input signal to the common mode voltage control loop. 17.The linear amplifier circuit of claim 16 wherein the common mode controlloop comprises a transistor pair arranged to receive a voltage controlmode input signal and a voltage reference signal, and to amplify adifference between the voltage control mode input signal and a voltagereference signal.
 18. The linear amplifier circuit of claim 1 whereinthe first and second amplifier components of the output stage are classAB linear amplifier components.
 19. The linear amplifier circuit ofclaim 1 wherein the output stage is arranged to provide a differentialsignal to a speaker.
 20. A semiconductor device comprising a linearamplifier circuit, according to claim 1.